A common requirement for an advanced electronic circuit and particularly for circuits manufactured as integrated circuits (“ICs”) in semiconductor processes is the use of static RAM (“SRAM”) memory cells for storage. More recently, embedded SRAM arrays are provided as part of integrated circuits that include other functions, such as radio transceivers, microprocessors, microcontrollers, processors, cell phone circuitry and the like to provide a system on a chip “SoC” device. Increasingly, the SRAM designs are provided as “cores” or “macros” that are included with other functionality on an integrated circuit such as an application specific integrated circuit (“ASIC”).
In order to properly determine the access time needed for read cycles, a timing generation circuit provides a word line (“W/L”) pulse of a certain duration. The timing of this pulse is very important to the power consumption, SRAM access speed, and efficient operation of the SRAM array. In any case, the goal is to make the W/L pulse long enough for proper operation, but not too long, which results in wasted power.
The operation of an SRAM depends on sense amplifiers which are coupled to the column or “bit lines”. The bit lines are coupled to the cells in order to provide the read data from (and write data to) the SRAM cells. An SRAM cell is often a 6 transistor cell which has two inverters coupled to form a latch. The cross coupled inverters will maintain a stored datum indefinitely so long as power is maintained to the device. In addition, a pair of pass gates couple the inverter latch to a true and a complement bit line. Because the SRAM cells are static memory cells, they need not be clocked or refreshed to maintain a stored datum. This makes SRAM storage very attractive and particularly useful in devices which have standby or “sleep” modes, including as embedded portions of the processors or other ICs for cellphones, PDAs, portable devices of all kinds, music and video players, etc. The device including the SRAM cells may enter a standby or low power mode for many cycles and then, when needed, processing may restart without any loss of data.
An SRAM read cycle begins with the bit lines, which are configured as pairs of true and complement data carrying lines, precharged or equalized to a common voltage, such as Vdd or Vdd/2. The bit lines are often referred to as “column lines” but the physical orientation or the SRAM layout does not affect the function of the lines. One common arrangement provides rows of cells coupled to and arranged on a common word line, and columns of cells arranged on a common pair of bit lines However, alternative arrangements such as diagonal and folded bit lines, and various other arrangements for the cell layouts are possible, so in this application the terms “word lines” and “bit lines” are used without regard to the direction, or relative layout arrangement, selected. When an active word line rises to an active level, the pass gates in a selected memory cells coupled to that word line become active and couple the paired bit lines to the SRAM cell, and to the stored data. The bit lines begin at a precharged level, but after the read cycle begins, one of the two bit lines in the bit line pair will begin to fall to a lower voltage level. However, as is known in the art, it is not necessary for the bit lines to fall to a logical low level voltage (such as Vss or zero volts) because small signal differential voltage sensing is used.
The sense amplifiers, which are a portion of the output or read circuits for the SRAM array, receive both of the bit lines of the bit line pair into a differential amplifier. The sense amplifier input circuit detects a small signal voltage difference between the bit line pair and then latches a data value that corresponds to the stored data in the SRAM cell. The sense amplifier also amplifies this small signal voltage to a full logic level output signal for use by external logic circuitry. Often an I/O circuit provides an output latch and output drivers. The output latch may be clocked to provide the data at a definite point in time, for use by the synchronous logic in the rest of the integrated circuit or system.
By using the small signal sensing, the sense amplifiers can rapidly determine the value on the bit lines and provide a full logic level output. Thus, the SRAM read cycle may be shortened in duration, because the small signal voltage difference on the bit lines that can be sensed correctly is only a few hundred millivolts. It is not necessary to extend the SRAM read cycle to the full time that would be needed to completely discharge the lower bit line of the pair; instead, it is only necessary to provide a read cycle of long enough duration to allow a sufficient small differential voltage to develop between the bit lines. The use of differential sensing thus greatly improves the data access time (speeds up the SRAM read cycle).
In order to ensure the word line pulse to the SRAM array is of sufficient duration to enable proper bit line separation during an SRAM read operation, but that the duration is not too long, SRAM tracking cells are conventionally used. In a conventional SRAM array, the tracking cells are parallel cells arranged in correspondence with the bit lines, so that the layout of the SRAM array is regular and compact. Thus the number of tracking cells is limited by the number of bit lines in the array, and the position of the tracking cells is limited by the layout of the array. The tracking cells are used to emulate the bit cells, and to provide an emulation of the loading on the word line and the bit lines. By providing the tracking circuits in the actual array, local variations (due to process variations in, for example, transistor drive or inter line capacitance) and global variations in different portions of the array can be emulated. However in conventional SRAM tracking cells used in SRAM arrays, the tracking time obtained does not emulate the real discharge time of the SRAM cell array. A. Global variations and local variations may not be accurately represented in the tracking circuit. As a result, word line pulse duration is often generated with extra margin (too much time) to ensure proper operation.
A continuing need thus exists for SRAM timing tracking circuits and methods that overcome the disadvantages of the prior art approaches. The tracking circuits should be compatible with existing semiconductor processes and circuits and be implemented without the need for added process steps or materials.
The drawings, schematics and diagrams are illustrative and not intended to be limiting, but are examples of embodiments of the invention, are simplified for explanatory purposes, and are not drawn to scale.